Method of patterning a submicron semiconductor layer

ABSTRACT

A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. An interlevel dielectric layer is formed over the surface of the integrated circuit. A planarizing layer is formed over the interlevel dielectric layer. A photoresist layer is formed and patterned over the planarizing layer. The planarizing layer is etched to form openings exposing selected portions of the interlevel dielectric layer, wherein each opening has the same lateral dimensions. The photoresist and planarizing layers are then removed. The interlevel dielectric layer is etched in the openings to expose portions of the underlying integrated circuit.

This is a continuation of prior application Ser. No. 08/205,830 filed onMar. 4, 1994, now abandoned which is a divisional of prior applicationSer. No. 07/828,734, filed on Jan. 31, 1992, now U.S. Pat. No.5,323,047.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor integratedcircuit processing, and more specifically to patterning a submicronsemiconductor layer.

BACKGROUND OF THE INVENTION

With the trend to continue to miniaturize semiconductor integratedcircuits to achieve submicron feature sizes, photolithography has becomeone of the most critical steps in semiconductor manufacturing. The goalof photolithography in establishing the critical dimensions of thevarious devices and circuits is to create a pattern which meets designrequirements as well as to correctly align the circuit pattern on thesurface of the wafer.

As line widths shrink smaller and smaller in submicron photolithography,the process of printing lines and contact holes in photoresist becomesincreasingly more difficult. Photoresists have been developed to keeppace with the industry's need to print narrower lines with fewerdefects. The selection of the photoresist must be made on whether thephotoresist has the capability of producing the design dimensions. Athinner resist layer will generally improve the capability of printingsmaller feature sizes. However, the resist must simultaneously be thickenough to act as an etchant barrier and be free of pinholes.

The smallest equal lines and spaces that can be formed in thephotoresist layer is known as the resolution capability. Thinnerphotoresist film thicknesses will improve the resolution capability.

As circuits increase in the number of layers, the wafer surface becomesless planar. The resolution of small image sizes is further reduced dueto the difference in the topography areas in which the photoresistthickness becomes uneven across the wafer surface. When the exposureradiation is directed at the wafer surface at a 90° angle to thesurface, a well-defined image is created in the photoresist because theexposing waves reflect up and down in the resist. If, however, any ofthe exposing radiation waves reflect at angles other than 90° up fromthe surface beneath the photoresist, unwanted portions of thephotoresist will be exposed. Variations in the subsurface topographyintensify the problem of reflection. The sidewalls of the steps, forexample, reflect the radiation at various angles, causing poor imageresolution. A smooth surface under the photoresist will eliminate muchof the reflection problems.

In addition, where the surface beneath the photoresist is uneven, theexposure time of the photoresist must be sufficient to expose thephotoresist at its thickest depth. This means that the thinner areas ofphotoresist will be over exposed, resulting in wider lateral openings ornarrower lines which will produce poorer image resolution.

It would be desirable to provide a fabrication technique having aplanarized surface beneath the photoresist layer to achieve better imageresolution and smaller image-size openings. It would further bedesirable for such technique to use a thin photoresist to achievesmaller line openings. It would also be desirable for such fabricationtechnique to be easily adapted for use with standard integrated circuitprocess flows.

SUMMARY OF THE INVENTION

The invention may be incorporated into a method for forming asemiconductor device structure, and the semiconductor device structureformed thereby, by forming a non-planar layer over the integratedcircuit. A planarizing layer is formed over the nonplanar layer. A thinphotoresist layer is formed and patterned over the planarizing layer,wherein the thickness of the photoresist layer is determined by the etchrate of the planarizing layer to the photoresist layer and the thicknessof the planarizing layer at the planarizing layer's thickest point. Theplanarizing layer is etched using the photoresist layer as a mask andthe nonplanar layer is etched using the planarizing layer as a mask.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are setforth in the appended claims. The invention itself, however, as well asa preferred mode of use, and further objects and advantages thereof,will best be understood by reference to the following detaileddescription of illustrative embodiments when read in conjunction withthe accompanying drawings, wherein:

FIGS. 1-10 are cross-sectional views of the fabrication of asemiconductor device structure according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The process steps and structures described below do not form a completeprocess flow for manufacturing integrated circuits. The presentinvention can be practiced in conjunction with integrated circuitfabrication techniques currently used in the art, and only so much ofthe commonly practiced process steps are included as are necessary foran understanding of the present invention. The figures representingcross-sections of portions of an integrated circuit during fabricationare not drawn to scale, but instead are drawn so as to illustrate theimportant features of the invention.

Referring to FIG. 1, an integrated circuit device is to be formed on asilicon substrate 10. A field oxide region 12 is formed on the substrateto separate active areas. A conductive structure such as a transistorgate is formed on the substrate by known methods comprising gateelectrode 14 disposed over a gate oxide 16. The transistor will alsocomprise oxide spacers 18 and source/drain regions 20. Anotherconductive structure 22 may be formed over the field oxide region 12such as a polysilicon signal line. An interlevel dielectric layer isformed over the integrated circuit. This layer may comprise an undopedoxide layer 24 typically having a thickness of between approximately1000 to 2000 angstroms. A conformal borophosphorous silicate glass(BPSG) layer 26 is formed over the oxide layer 24. Layer 26 willtypically have a thickness of between approximately 5000 to 6000angstroms.

Referring to FIG. 2, an etch stop layer 28 if formed over the conformalinterlevel dielectric layer 24, 26. The etch stop layer 28 may formedfrom any material suitable for semiconductor processing which has a highetch selectivity to oxide. Layer 28 will typically have a thickness ofbetween approximately 500 to 1000 angstroms. Preferably, layer 28comprises titanium nitride or tantalum disilicide. A planarizing layer30 such as spin-on-glass (SOG) is formed over the etch stop layer 28. IfSOG is used, it may be cured to form a planarized silicon dioxide film.Layer 30 will typically have a nominal thickness of betweenapproximately 5000 to 7000 angstroms. The thickness of layer 30 willdepend upon the topography of the underlying non-planar layer 28. A thinphotoresist layer 32 is formed over the planarizing layer 30.

Referring to FIG. 3, the photoresist layer 32 is patterned to formopenings 34. The planarizing layer 30 is etched away in opening 34 usinglayer 28 as an etch stop. Referring to FIG. 4, the etch stop layer 28 isetched in opening 34 exposing the BPSG layer 26 in the opening.

Referring to FIG. 5, the photoresist layer 32 and the planarizing layer30 are removed exposing the etch stop layer 28. The removal of thephotoresist layer 32 may be done by a plasma oxygen etch process. Theremoval of the planarizing layer 30 may be done in a dilutedhydrofluoric acid solution.

Referring to FIG. 6, the interlevel dielectric layer comprising oxidelayer 24 and BPSG layer 26 is etched in the openings 34 exposing theactive areas beneath the layer. For example, the gate electrode 14,source/drain region 20 and gate or signal line 18 are exposed. Aconductive layer 36 is then formed over the etch stop layer 28 and inthe openings 34 making contact with the underlying conductivestructures. The etch stop layer 28 may be removed before the conductivelayer 36 is formed.

Referring to FIG. 7, the BPSG layer 26 may first be isotropically etchedto form sloped sidewalls 36a in the openings 34 toward the upper portionof the sidewall. An anisotropic etch is then performed to form thevertical sidewalls through the lower portion of the BPSG layer 26 andthe underlying oxide layer 24. If an isotropic etch is first performed,the etch stop layer 28 is removed after the interlevel dielectric layeris etched exposing portions of the active areas underlying theinterlevel dielectric layer. A conductive layer 36 is then formed overthe interlevel dielectric layer and in the openings 34 as shown in FIG.8. The sloped sidewalls will improve step coverage of the conductivelayer into the openings 34.

Referring to FIG. 9, an alternative embodiment is shown. An integratedcircuit device is to be formed on a silicon substrate 40. A field oxideregion 42 is formed on the substrate to separate active areas. An oxidelayer 44 is formed over the integrated circuit. A conformal conductivelayer 46 is formed over the oxide layer 44. The conformal layer 46 maybe a doped polysilicon or a layer such as a polycide. A planarizinglayer 48 is formed over the conformal conductive layer 46. Theplanarizing layer may be a spin-on-glass which has a sufficientthickness to be substantially planar across an upper surface. A thinphotoresist layer 50 is formed on the planarizing layer 48. Thephotoresist is patterned to form openings 52.

Referring to FIG. 10, the planarizing layer 48 is etched in the openings52 using the photoresist layer 50 as a mask. The conformal layer 46 actsas an etch stop during the etching of the planarizing layer 48. Theconformal layer 46 is then etched using the planarizing layer 48 as amask. The conformal layer remaining may be, for example, a gateelectrode 54 of a transistor or a signal line 56. In forming theplanarizing layer 48 between the conformal layer and the photoresist, athinner photoresist can be used which provides for smaller imageresolution and uniform dimensions.

The planarization of the layer 30, as shown in FIG. 2, also allows for athin layer of photoresist 32 to be used. Reflection problems from layer30 are minimized because there is no varying topography to reflect theexposure radiation at different angles. Using a thin photoresist,smaller lines and smaller openings can be uniformly made across thesurface of the planarizing layer 30. This will improve the resolutioncapability, as shown in FIG. 3. The resolution capability of thephotoresist can be expressed as: ##EQU1##

The wavelength and numerical aperture values are fixed values determinedby the exposure tools used in the process. Thus, the resolution can beimproved or made smaller by lowering the K factor. The K factor islowered as the photoresist layer is made thinner. The thickness of thephotoresist is determined by the etch selectivity of the planarizinglayer to the photoresist layer and the thickness of the planarizinglayer at its thickness point as shown in the center opening 34 in FIG. 3and reference numeral 58 in FIG. 10. For example, if the etchselectivity of the planarizing layer to the photoresist layer is 2:1 andthe depth of the planar layer at its thickest point is 4000 angstroms,then the photoresist layer must be at least 2000 angstroms thick. Anyadditional thickness of the photoresist layer will decrease the imageresolution but may insure that the photoresist layer is pinhole free.

The etch stop layer 28, shown in FIG. 3, will act as an etch stop duringthe etching process of the planarizing etch stop layer 30. If layer 28were absent, the depth of the planarizing layer would be greater becausethe etch process would continue through the interlevel dielectric layer24, 26. With the etch stop layer 30 present, the thickest point of theplanarizing layer 30 is minimized, thus allowing for a thinnerphotoresist layer 32 and better image resolution. The result is that thebest possible image resolution can be achieved while the horizontaldimensions of each of the contacts or vias can be made uniform.

As will be appreciated by those skilled in the art, the process stepsdescribed above can be used with nearly any conventional process flow.While the invention has been particularly shown and described withreference to a preferred embodiment, it will be understood by thoseskilled in the art that various changes in form and detail may be madetherein without departing from the spirit and scope of the invention.

What is claimed is:
 1. A method of patterning a submicron layer for asemiconductor integrated circuit, comprising the steps of:forming aninterlevel dielectric layer over the surface of the integrated circuit;forming an etch stop layer over the interlevel dielectric layer, whereinthe etch stop layer has an etch selectivity to the interleveldielectric; forming a planarizing layer over the interlevel dielectriclayer; forming a photoresist layer over the planarizing layer to athickness not substantially greater than a thickness of the planarizinglayer at a thickest point to be etched times an etch selectivity of theplanarizing layer to the photoresist layer; patterning the photoresistlayer to expose portions of the planarizing layer; etching theplanarizing layer to form openings exposing selected portions of theetch stop layer; etching the exposed portions of the etch stop layer toform openings which expose selected portions of the interleveldielectric layer; removing the photoresist layer and the planarizinglayer; and after removing the photoresist layer and the planarizinglayer, etching the interlevel dielectric layer in the etch stop layeropenings to form openings through the interlevel dielectric layer whichexpose portions of the underlying integrated circuit.
 2. The method ofclaim 1, wherein the interlevel dielectric layer comprises a BPSG layerdisposed over an undoped oxide layer.
 3. The method of claim 2, whereinthe etch stop layer comprises tantalum disilicide.
 4. The method ofclaim 2, wherein the etch stop layer comprises titanium nitride.
 5. Themethod of claim 1, wherein the planarizing layer comprises aspin-on-glass layer having a thickness of between 5000 to 7000angstroms.
 6. The method of claim 1, wherein the planarizing layer iscured after it is formed.
 7. The method of claim 1, further comprisingthe steps of:isotropically etching a portion of the interleveldielectric layer to form sloped sidewalls toward an upper portion of theinterlevel dielectric layer; anisotropically etching the interleveldielectric layer to form vertical sidewalls from a bottom portion of thesloped sidewalls to an upper surface of the exposed portions of theunderlying integrated circuit.
 8. The method of claim 1, furthercomprising the steps of:removing the etch stop layer after theinterlevel dielectric layer is etched.
 9. The method of claim 1, whereinthe thickness of the photoresist layer depends upon the etch selectivityof the planarizing layer to the photoresist layer and the thickness ofthe planarizing layer at the planarizing layer's thickest point.
 10. Themethod of claim 1, further comprising the step of:forming a conductivelayer over the etch stop layer and in the openings through theinterlevel dielectric layer after the interlevel dielectric layer isetched.
 11. A method of patterning a submicron layer for a semiconductorintegrated circuit, comprising the steps of:forming an interleveldielectric layer over the surface of the integrated circuit; forming anetch stop layer over the interlevel dielectric layer, wherein the etchstop layer has an etch selectivity to oxide; forming a planarizing layerover the interlevel dielectric layer; forming a photoresist layer overthe planarizing layer to a thickness not substantially greater than athickness of the planarizing layer at a thickest point to be etchedtimes an etch selectivity of the planarizing layer to the photoresistlayer; patterning the photoresist layer to expose portions of theplanarizing layer; etching the planarizing layer to form openingsexposing selected portions of the etch stop layer, wherein openings inthe planarizing layer have substantially the same lateral dimensions;etching the etch stop layer exposed in the openings in the planarizinglayer to form openings in the etch stop layer which expose selectedportions of the interlevel dielectric layer; removing the photoresistlayer and the planarizing layer; after removing the photoresist layerand the planarizing layer, etching the interlevel dielectric layer inthe openings in the etch stop layer to form openings in the interleveldielectric layer which expose portions of the underlying integratedcircuit; and forming a conductive layer over the interlevel dielectriclayer and in the openings in the interlevel dielectric layer to form acontact.